Microprocessor architectures, C, and C++ programming languages. Basic knowledge in VHDL or Verilog languages.

The main purpose of the course is to present the abstractions applied in complex digital system design and to demonstrate how the different formal languages (high level programming languages and hardware description languages) may be used in modeling, design, and functional verification of digital systems.

After discussing the characteristics of the abstraction levels and optimization goals of complex digital system design, the different formal language means of high level programming techniques such as procedural and object-oriented paradigms are presented by instruction set simulator examples. The Register-Transfer Level (RTL) modeling is the central topic of the second part of the semester. This part of the course also demonstrates the SystemC-based HW/SW co-design paradigm and the methods applied in cycle-accurate modeling using SystemC, furthermore, the techniques used in synthesizable VHDL modeling is discussed as well by presenting the synthesizable VHDL implementations of the exemplary instruction set simulators. The course provides an overview of the implementation techniques of complex digital circuits, namely the standard cell ASIC, CPLD and FPGA technologies. In the last part of the semester the modern functional verification methodologies are discussed, such as e language and eRM verification.

Week 1.: Abstraction levels in the digital system modeling
Week 2.: Algorithmic modeling of microprocessors: procedural approach
Week 3.: Algorithmic modeling of microprocessors: object-oriented approach
Week 4.: Overview of VHDL: synthesizable language constructs for RTL modeling
Week 5.: VHDL-based RTL design
Week 6.: RTL optimization I.: basics
Week 7.: RTL optimization II.: Clock Domain Crossing (CDC), Reset
Week 8.: RTL optimization III.: datapath optimization: resource requirement, timing, power-consumption
Week 9.: RTL modeling of microprocessors
Week 10.: Overview of SystemC, creating cycle-accurate models from procedural algorithmic models using SystemC wrappers
Week 11.: Implementation technologies: stdcell ASICs, CPLDs, FPGAs
Week 12.: ASIC verification I.: basics
Week 13.: ASIC verification II.: eRM verification methodology
Week 14.: Mid-semester check

2 hours/week lectures.

a. Optional homework

One mid-semester check

b. Requirement for granting the signature: mid-semester check grade >= 2 (satisfactory)

c. Mid-term grade: mid-semester check grade modified by the additional points of the optionally submitted homework

Two repeated checks in the repeat period.

By appointment with the lecturer.

1. Slides accessible on the web. Additional lecture material and source codes prepared by the lecturer.